The present invention relates to memory cell circuits for random access memories and, more particularly, to memory cell circuits based on bipolar transistors.
Digital memories of various kinds are used extensively in computers and computer system components, digital processing systems, and the like. This increasing use has been made possible primarily by the rapid shrinking in size of monolithic integrated circuits that has been occurring in recent years. Such shrinkage has allowed an increase in the density of circuits provided in monolithic integrated circuit chips, and this has both improved performance and reduced cost.
Memory cell circuits based on bipolar transistors have been used primarily because of the speed of operation obtainable with such transistors. However, the advent of merged complementary bipolar transistor structures has permitted fabricating bipolar transistor memories also having a substantial density of memory cells in a monolithic integrated circuit chip.
A typical merged transistor circuit for a memory cell has a pair of pnp bipolar transistors serving as loads, and has a further pair of cross-coupled npn bipolar transistors serving as the control transistors for operating the memory cell circuit. The emitters of the pnp bipolar transistors are connected to the memory system word line interconnection extending from the address decoding circuitry, and the emitters of the npn bipolar transistors are connected to the memory system standby line interconnection also extending from the same decoding circuitry. Each control transistor has its collector connected to the other's base and to both the base of one pnp load transistor and to the collector of the other pnp load transistor.
In those situations in which the memory cell is not to have information stored therein or retrieved therefrom, the cell is in the standby mode of operation and reduced voltages are applied to both the word line and the standby line to which the cell is connected. An increase in the voltages of these two lines occurs selectively, occurring in response to an appropriate address being presented to the memory indicating the row of memory cells in which the cell of interest is located. This increase in voltage will permit storing or retrieving information from the memory cell.
A bit line is typically connected through a switching device of a suitable kind to the collector of each control transistor. The arrangement is configured in such a manner so as to permit storing information in the memory cell through these bit lines or retrieving information therefrom over these bit lines.
In operation, one of the control npn bipolar transistors is in the "on" condition, as is its pnp bipolar transistor load. The other control npn bipolar transistor is in the "off" condition, as is also its pnp transistor load. Current thus flows through one side, and not the other, to thereby set the state of the memory cell and so the information it contains.
Such a memory cell has a drawback, however, because the two transistors in the "on" condition are as a result each operated so as to be well into the saturation region thereof. This results in the storage of charge carriers in each of the base regions thereof, and so the switching time of such a pair of transistors from the "on" condition to the "off" condition is slowed. Such a slowing of switching time means that information cannot be stored in the memory cell as quickly as it might otherwise be, thus slowing the operation of the memory. Slowing of the operation of the memory, in turn, slows the operation of the system in which the memory is used.
One improvement that can be made in such a memory cell is to have each of the pnp transistors provided with a second collector connected to its base. This in effect then provides current from both the base and the collector of the pnp load transistor to the collector of the npn control transistor rather than from just base of this pnp load transistor. This reduces the base current required from the pnp load transistor, and correspondingly limits the saturation of the pnp load transistor. Since this pnp bipolar transistor is then operated drawing less base current therethrough, there is less current flowing out of the other collector thereof into the base of its control npn bipolar transistor thereby reducing its saturation.
This reduction in saturation aids in permitting the memory cell to operate faster. However, there still remains operation of the "on" condition transistors in substantial saturation, and so there is a desire to reduce such saturation further to permit a greater increase in the rapidity of operation of the memory cell.